Available · Fall 2026 Co-op

Deepansh
Sabharwal

Computer Engineering, UBC.
I build things with clock signals.

RTL-level FPGA design, bare-metal RISC-V, hardware-software integration, and edge AI on embedded hardware. If it runs on silicon, I want to understand it from the ground up.

FPGA · Gowin GW2A-LV18 IDLE
LUT LUT LUT LUT ROUTING FABRIC FF FF DSP IO CLK
Fmax
Util
RTL / Verilog
·
RISC-V
·
Embedded C
·
Edge AI
·
HW–SW Integration
·
Computer Vision
·
Flask / REST
·
OpenCV

What I've built.

Real problems, real hardware. Five projects across RTL design, embedded systems, hardware-software integration, and applied ML.

Hardware Flask 2025

ThermoGuard Safety System

Hardware-software integration across four layers: Arduino reads a thermal sensor, communicates over UART to a Raspberry Pi, which runs a Flask REST API surfacing live data to a web frontend. Temperature threshold breach triggers real hardware alerts. A single unbroken data path from sensor to screen.

Edge AI Research 2026

Wildlife Collision Warning System

Solar-powered roadside node: FLIR thermal camera → YOLOv8-nano on Jetson Orin NX via TensorRT, no cloud dependency. Detection events route over LoRaWAN to dynamic warning signs via GPIO — sub-second from animal to alert. Submitted to BC Ministry of Transportation for Hwy 97 Okanagan, April 2026.

RISC-V Bare-metal 2025

RISC-V Toolchain to Emulation

End-to-end bare-metal pipeline: C → cross-compiled RISC-V ELF → OpenSBI M-mode boot → privilege transitions via riscv-pk → 64-bit QEMU. Every layer understood, not black-boxed. Next phase: Tang Nano 20K physical deployment as a soft core.

Hardware EV 2024

CyberTrike

RC three-wheeled EV prototype, schematic to rolling chassis in one term. Owned the full electrical path: Arduino PWM motor control, hand-drawn circuit schematics on protoboard, NRF24L01 wireless remote. Single-rail power routing, conservatively margined. Prototype drove. Lesson learned: start with a PCB.

The short version.

Second-year Computer Engineering at UBC. I build things that run at the metal level — FPGA state machines, RISC-V pipelines, edge AI nodes on thermal cameras. Not for the difficulty, but because the feedback loop between a design decision and observable silicon behaviour is the most honest form of engineering I know.

Active research: a solar-powered thermal-camera wildlife detection node for BC highways. Ongoing: deploying the RISC-V pipeline as a physical soft core on a Tang Nano 20K. When I'm not in the lab, I'm reading about what I don't understand yet.

Status Available · Fall 2026 co-op
Program B.A.Sc. Computer Engineering, UBC
Location Kelowna, BC · UTC-7 · Open to relocation
Languages English · Hindi · Punjabi
RTL / Verilog / FPGA
RISC-V / ISA
Embedded C / Firmware
HW–SW Integration
Edge AI / TensorRT
Python / Flask / REST
OpenCV / Computer Vision
Cert. Mastering OpenCV with Python — OpenCV University, Dec 2025

Let's talk hardware.

Actively looking for co-op positions in embedded systems, FPGA design, firmware, and edge AI — starting September 2026. If you're building something real on silicon, reach out.

Response Within 48 hours, weekdays, UTC-7