Seeking Fall 2026 Co-op - Embedded Systems, FPGA, Firmware, Edge AI
Computer Engineering @ UBC
I build systems where hardware and software meet - from RTL-level FPGA design and bare-metal RISC-V pipelines to thermal-camera CV inference running on embedded hardware in the field. Second-year Computer Engineering at UBC, pursuing co-op in embedded engineering, FPGA development, and applied AI.
A deterministic, hardware-enforced PWM controller implemented in Verilog on the GW2A-LV18 FPGA (Tang Nano 20K). Fault handling and safe-state enforcement at the RTL level - no software override path.
The system generates a 32-bit configurable PWM signal for motor control and embedded actuation. A guard module validates period and duty constraints directly in hardware before enabling output. Any violation drives the FSM into a latched FAULT state that requires an explicit recovery sequence to exit.
Output latched LOW in FAULT. No software recovery path.
Full bare-metal compilation and emulation pipeline: C source → cross-compiled RISC-V ELF → 64-bit virtual RISC-V machine via QEMU, running without a conventional OS.
Used GCC cross-compiler to produce RISC-V ELF binaries, with OpenSBI and riscv-pk managing boot flow and privilege transitions. Analyzed the complete pipeline - ELF generation, ISA targeting, boot sequences, and hardware emulation - to build ground-up understanding of instruction set architecture and firmware-hardware interaction. Next phase targets physical deployment on Tang Nano 20K FPGA.
ML model predicting soil suitability for crop growth from environmental inputs - temperature, humidity, rainfall, wind speed, soil moisture. Logistic regression with cross-validation and an interactive decision interface for farmers.
RC-controlled 3-wheeled EV prototype at UBC. Led the electrical sub-team: PWM motor control, circuit schematics, protoboard power routing, and NRF radio module integration for reliable remote control.
Real-time weather web app using Python and REST API integration. Displays live temperature, humidity, and pressure data from weather APIs with a clean user interface.
Research proposal for a solar-powered edge AI node using a FLIR thermal camera and YOLOv8-nano on Jetson hardware to detect and classify large animals approaching a road in real time - triggering dynamic LED warning signs with no cloud dependency. Addresses a documented gap in North American RADS: no deployed system uses on-device CV to classify animals. Target corridor: Hwy 97, Okanagan.
Second-year Computer Engineering student at UBC. My work covers both sides of the hardware-software boundary: writing Verilog state machines on physical FPGAs, building bare-metal RISC-V compilation pipelines, training ML models on real datasets, and wiring circuits on physical prototypes.
I pursue co-op roles in embedded systems, FPGA engineering, firmware, and edge AI, where hardware is a real constraint, not an abstraction. Timing closure, silicon area, power budget, and thermal limits are the environment I work in.
Active research: a solar-powered thermal-camera wildlife detection system proposed to BC Ministry of Transportation, targeting the Hwy 97 Okanagan corridor. In parallel, progressing toward physical FPGA deployment of the RISC-V pipeline on Tang Nano 20K.
Open to co-op positions in embedded systems, FPGA engineering, edge AI, and software development starting September 2026.